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Features

The UN331C controls the system and executes stored programs that perform call processing activity and maintenance. The UN331C is a RISC designed around a MIPS R3000A CPU operating at 33 MHz. It employs 32-bit address and data buses to obtain and execute instructions at a rate approaching 1 instruction per clock cycle. The 256 kbyte instruction cache with burst-mode refill and 256 kbyte data cache are key to the performance of the processor. A read/write buffer chip tailors the UN331C to the call processing environment.

Peripheral devices residing on the UN331C are positioned outside the CPU cache structure and interface to the CPU through the read/write buffers. These peripherals include 512 kbytes of ROM for the monitor, counters/timers, UARTs, control/status/error registers, and the logic that provides bus arbitration and the Bus Time-Out feature.

Includes

 

Refurbished

Library

Avaya-Definity-Server-R-Upgrades-and-Additions.pdfAvaya Definity Server R Upgrades and Additions.pdf
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